1) How are the instructions executed in DSP Processors?
a. In Parallel manner
b. In Sequential manner
c. Both a and b
d. None of the above
|
Answer
Explanation
|
ANSWER: In Parallel manner
Explanation:
No explanation is available for this question!
|
|
2) In TMS 320 C5X processor, which memory segment provides interfacing to external memory mapped peripherals and also serves as extra data storage space?
a. Program Memory
b. Data memory
c. I/O Memory
d. All of the above
|
Answer
Explanation
|
ANSWER: I/O Memory
Explanation:
No explanation is available for this question!
|
|
3) In TMS 320 C5X processor, which operation/s is/are performed by Compare Select & Store Unit (CSSU)?
a. Selection of large word in accumulator for storing into the data memory
b. Comparison between high & low word of accumulator
c. Maintain the record of transition histories
d. All of the above
|
Answer
Explanation
|
ANSWER: All of the above
Explanation:
No explanation is available for this question!
|
|
4) In ADSP 21 xx architecture, how many previously executed instructions are stored in instruction cache of cache memory?
a. 4
b. 8
c. 16
d. 32
|
Answer
Explanation
|
ANSWER: 16
Explanation:
No explanation is available for this question!
|
|
5) Match the following STKY multiplier (MAC) flag notations with their meanings in ADSP 21 xx family architecture.
A. MOS ------------------ 1) Multiplier floating-point invalid operation
B. MIS ------------------- 2) Multiplier Underflow
C. MUS ------------------ 3) Multiplier floating-point overflow
D. MVS ------------------ 4) Multiplier fixed-point overflow
a. A-3, B-2, C-4, D-1
b. A-2, B-3, C-1, D-4
c. A-1, B-4, C-3, D-2
d. A-4, B-1, C-2, D-3
|
Answer
Explanation
|
ANSWER: A-4, B-1, C-2, D-3
Explanation:
No explanation is available for this question!
|
|
6) In ADSP 21xx architecture, which notation represents ALU overflow condition?
a. AC
b. AV
c. NE
d. EQ
|
Answer
Explanation
|
ANSWER: AV
Explanation:
No explanation is available for this question!
|
|
7) In CPU structure, what kind of instruction to be executed is held by an instruction Register (IR)?
a. Current (present)
b. Previous
c. Next
d. All of the above
|
Answer
Explanation
|
ANSWER: Current (present)
Explanation:
No explanation is available for this question!
|
|
8) In CPU structure, which register provides the address for fetching of data or instruction especially by means of processor?
a. Data Register
b. Instruction Register
c. Accumulator
d. Memory Address Register
|
Answer
Explanation
|
ANSWER: Memory Address Register
Explanation:
No explanation is available for this question!
|
|
9) In CPU structure, where is one of the operand provided by an accumulator in order to store the result?
a. Control Unit
b. Arithmetic Logic Unit
c. Memory Unit
d. Output Unit
|
Answer
Explanation
|
ANSWER: Arithmetic Logic Unit
Explanation:
No explanation is available for this question!
|
|
10) In Von Neumann architecture, which among the following handles all the operations of the system that are inside and outside the processor?
a. Input Unit
b. Output Unit
c. Control Unit
d. Memory Unit
|
Answer
Explanation
|
ANSWER: Control Unit
Explanation:
No explanation is available for this question!
|
|
